Whole Sky Technologies / Dewdrop: Hardware Enforcement of Memory Safety and More at a Modest Cost

Opportunity: “A New Golden Age for Computer Architecture”

We see opportunity in a confluence of the following two facts:

70% of computer security is one problem, memory safety, and
hardware has become soft, so small players can now participate in chip design.

Microsoft & Google: 70% of computer security failures are memory safety failures

Microsoft, June 2019: https://msrc-blog.microsoft.com/2019/07/18/we-need-a-safer-systems-programming-language/

[T]he root cause of approximately 70% of security vulnerabilities that Microsoft fixes and assigns a CVE (Common Vulnerabilities and Exposures) are due to memory safety issues [since at least 2006]. This is despite mitigations including intense code review, training, static analysis, and more….

While many experienced programmers can write correct systems-level code, it’s clear that no matter the amount of mitigations put in place, it is near impossible to write memory-safe code using traditional systems-level programming languages at scale.

Google, May 2020: https://www.zdnet.com/article/chrome-70-of-all-security-bugs-are-memory-safety-issues/

Roughly 70% of all serious security bugs in the Chrome codebase are memory management and safety bugs, Google engineers said this week.

Hardware has become soft

Hardware has become “soft” and there will now be an explosion in innovation in hardware similar to that which there has been in recent decades in software.

David Patterson at his 10 October 2018 Turing Award talk at Berkeley said https://eecs.berkeley.edu/turing-colloquium/schedule/patterson

The ending of Dennard scaling and Moore’s law and the deceleration of performance gains for standard microprocessors are not problems that must be solved but facts that if accepted offer breathtaking opportunities. We believe high-level, domain-specific languages and architectures, freeing architects from the chains of proprietary instruction sets, and the demand from the public for improved security will usher in a new Golden Age for computer architecture. Aided by open source ecosystems, agilely developed chips will convincingly demonstrate advances and thereby accelerate commercial adoption. The instruction set philosophy of the general-purpose processors in these chips will likely be RISC, which has stood the test of time. We envision the same rapid improvement as in the last Golden Age, but this time in cost, energy, and security as well as in performance. Like the 1980s, the next decade will be exciting for computer architects in academia and in industry!

It is financially feasible for a startup to make an ASIC: Hennessy and Patterson in their February 2019 Turing Award talk "A New Golden Age for Computer Architecture" https://cacm.acm.org/magazines/2019/2/234352-a-new-golden-age-for-computer-architecture/ said

Many researchers assume they must stop short because fabricating chips is unaffordable. When designs are small, they are surprisingly inexpensive. Architects can order 100 1-mm² chips for only $14,000. In 28 nm, 1 mm² holds millions of transistors, enough area for both a RISC-V processor and an NVLDA accelerator. The outermost level is expensive if the designer aims to build a large chip, but an architect can demonstrate many novel ideas with small chips.

Patterson in “A New Golden Age for Computer Architecture” https://cacm.acm.org/magazines/2019/2/234352-a-new-golden-age-for-computer-architecture/ : Several recent technology changes making it orders of magnitude easier to design and deploy computer hardware have made a perfect storm for a fundamental shift in the computing industry:

high-level languages like Chisel,
the continuing drop in the price to fabricate an ASIC and the decreasing price and increasing capability of FPGAs (special purpose hardware simulators) to the point where people are deploying solutions on them rather than just using them for design, and
the development of a viable Open Source RISC instruction set architecture, RISCV.